The present invention relates to a semiconductor memory device as a memory cell of an electrically erasable and programable read-only memory (EEPROM).
Significant development has been made in EEPROMs due to their unique non-volatility and in-system reprograming capability. An EEPROM generally has a number of memory cells arranged in a matrix form; each memory cell stores either logic value "H" or "L". FIG. 1 shows a conventional memory cell which uses a Fowler-Nordheim tunneling current for programing and erasing information. Such a memory cell is introduced, for example, in IEEE J. of Solid-State Circuits. Vol. SC-17, No. 5, Oct. 1982, p. 821. This memory cell has a transistor 10 having a floating gate for charging carriers and a transistor 12 rendered conductive when the memory cell is used. FIG. 2 is a plan view showing the arrangement of the memory cell, and FIG. 3 is a cross-sectional view along the line I--I in FIG. 2. The memory cell has n-type semiconductor regions 16, 18 and 20 formed in the surface area of a p-type semiconductor substrate 14. A channel region 24 is present between the regions 16 and 18, and the regions 16, 24 and 18 constitute a current path of the transistor 10 (FIG. 1). A channel region 26 is present between the regions 18 and 20, and the regions 18, 26 and 20 constitute a current path of the transistor 12 (FIG. 1). The channel region 24 is covered with a thin insulating layer 28 for tunneling carriers. A conductive layer 30 used as a floating gate of the transistor 10 is formed on the layer 28. The conductive layer 30 extends in a direction perpendicular to the direction of arrangement of the regions 16, 24 and 18, as shown in FIGS. 2 and 3. The conductive layer 30 is covered with an insulating layer 32 through which the carriers cannot tunnel. A conductive layer 34 used as a control gate of the transistor 10 is formed on the insulating layer 32 so as to overlap the conductive layer 30. A conductive layer 38 used as a select gate of the transistor 12 is formed on the channel region 26 through an insulating layer 36 having a thickness of about 700 .ANG.. The regions 16, 24, 18, 26 and 20 are arranged in a line in the surface area of the substrate 14. The semiconductor regions 16 and 20 are respectively connected to a common source line and a bit line (not shown), and the layers 34 and 38 are respectively connected to a control line and a word line (not shown).
In the erasing operation of the memory cell, while the transistor 12 is rendered conductive by a voltage from the word line, a low level voltage (0 V) is applied to the drain of the transistor 10 through the bit line, and a high level voltage (20 V) is applied to the control gate of the transistor 10 through the control line. Carriers are then accumulated in the floating gate of the transistor 10 increasing the threshold voltage of the transistor 10.
In the programing operation, while the transistor 12 is rendered conductive by a voltage applied through the word line, a high level voltage (20 V) is applied to the drain of the transistor 10 through the bit line, and a low level voltage (10 V) is applied to the control gate of the transister 10 through the control line. Then, the carriers are discharged from the floating gate of the transistor 10, and the threshold voltage of the transistor 10 is decreased.
The floating gate voltage VFG of the transistor 10 is given by the following approximation (see FIG. 4): EQU VFG.perspectiveto.(CT2.multidot.VG+CT1.multidot.VC)/(CT1+CT2)+QF/(CT1+CT2) (1)
where
CT1: capacitance between the channel region 24 and the floating gate 30 PA1 CT2: capacitance between the floating gate 30 and the control gate 34 PA1 QF: charge amount in the floating gate 30 PA1 VG: control gate voltage PA1 VC: drain voltage PA1 q: charge PA1 h: Planck's constant PA1 .phi.: band gap PA1 m: electron mass PA1 E: electric field in layer 28 PA1 d2: thickness of insulating layer 32 PA1 AT1: area of that portion of conductive layer 30 which is overlapped with channel region 24 through insulating layer 28 PA1 AT2: area of that portion of conductive layer 30 which is not overlapped with channel region 24 through insulating layer 28.
When it is assumed that QF=0 (C) and VC=0 (V), the floating gate voltage VFG1 when erasing is initiated is given by: EQU VFG1=(CT2.multidot.VG)/(CT1+CT2) (2)
When it is assumed that VG=0 (V), the floating gate voltage VFG2 when programing is started is given by: EQU VFG2=(CT1.multidot.VC)/(CT1+CT2)+QF/(CT1+CT2) (3)
In order that the memory cell operate properly, the value of VFG1 is preferably large and the value of VFG2 is preferably small. Especially when the high and low levels of the control gate voltage VG, and the high and low levels of the drain voltage VC are set to be equal to each other, the following relation must be satisfied: EQU CT2&gt;&gt;CT1 (4)
Generally, the ratio CT2/CT1 is 2 to 3. The smaller the level ranges between high and low levels of the control gate voltage VG and of the drain voltage VC, respectively, the smaller the transistor elements. Then, the operation reliability and manufacturing yield of EEPROMs as LSIs are improved.
The density JFN of tunnel current flowing through the thin insulating layer 28 is given by: EQU JFN=(q.sup.3 E.sup.2 /8.pi.h.phi.) exp (-4(2m).sup.1/2 .phi..sup.3/2 /3hqE) (5)
where
The density JFN of tunnel current increases proportionally with the electric field E. The condition for charging the carriers in the floating gate 30 is that the absolute value of a current I1 flowing in the insulating layer 28 is larger than that of a current I2 flowing in the insulating layer 32 (.vertline.I1.vertline.&gt;.vertline.I2.vertline.). Then, the absolute value of an electric field E1 in the insulating layer 28 must be larger than that of an electric field E2 in the insulating layer 32 (.vertline.E1.vertline.&gt;.vertline.E2.vertline.).
When VC=0 (V) and QF=0 (V), the ratio E1/E2 is given by: ##EQU1## where d1: thickness of insulating layer 28
In the relation (6) above, the condition CT2&gt;&gt;CT1 is applied utilizing the relation C=.epsilon.A/d (where C: capacitance; .epsilon.: dielectric constant; A: area of conductor; and d: thickness of insulator).
In the memory cell as described above, the insulating layer 28 is formed of monocrystalline silicon having a thickness of about 100 .ANG. so that many carriers can tunnel through the layer 28 upon application of a floating gate voltage of about 20 V. The conductive layer 30 is formed of polycrystalline silicon. The insulating layer 32 is formed of polycrystalline silicon oxide and has a thickness of about 800 .ANG..
The crystal grain orientation in the layers 30 and 32 is largely dependent on the manufacturing process, and considerable asperity is present at the interface between the layers 30 and 32. Since the asperity accelerates concentration of an electric field, the tunnel current is affected thereby, as may be seen from the relation (6) above. Thus, the memory cell as described above has low reliability with respect to its electrical characteristics, and presents a problem of low yield in the manufacture of EEPROMs.
When the thickness of the insulating layer 32 is set to be less than 800 .ANG., the above problems become more serious, and an improvement in the cell density cannot be expected with the same design rule. For example, when a memory cell having a ratio CT2/CT1 of about 2.7 is laid out in accordance with the 2 .mu.m design rule as shown in FIG. 5, the memory cell including the transistor 12 requires an area of 272 .mu.m.sup.2. An area AT1+AT2 of the conductive layer 30 as the floating gate is obtained as follows: EQU (AT1+AT2)/AT1=21.6 EQU AT1=W.times.L=2.times.1.5=3[.mu.m.sup.2 ], (W: channel width, L: channel length) EQU AT1+AT2=AT1.times.21.6=3.times.21.6=64.8[.mu.m.sup.2 ]